Field of the Invention
The present invention relates to a nonvolatile memory device, and more specifically to a function to prevent a writing error in the nonvolatile memory device.
Background Art
FIG. 3 is a block diagram of a writing circuit in a conventional nonvolatile memory device.
A conventional writing circuit 40 includes a control circuit 41, a clock counter 42, an overrun detection circuit 43, a status register 44, and an output circuit 45.
In a nonvolatile memory device that performs communication through a serial interface, data are written to memory cells as follows: Clocks are input to a clock (SCK) terminal after a chip select (CS) signal is validated, and a write command, an address, and write data are input sequentially to a data input (DI) terminal concurrently. Then, when a predetermined write time has elapsed since the CS signal was invalidated, data write processing to memory cells is ended.
The overrun detection circuit 43 compares a prescribed number of clocks acquired from the control circuit 41 with an actual number of clocks acquired from the clock counter 42. Here, when noise is mixed into the SCK terminal to make the number of clocks larger than the prescribed number, the overrun detection circuit 43 detects an overrun, and sets an overrun detection flag in the status register 44. Then, the nonvolatile memory device cancels the write processing.
The overrun detection flag in the status register 44 can be output to a data output (DO) terminal through the output circuit 45 to let an external master side recognize the clock overrun. Then, since the overrun detection flag is reset by inputting the CS signal again or the like, the master can retry the write processing.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2005-71512